1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof, and particularly to a semiconductor device having a plurality of circuit parts with different structures, like a memory cell part and logic circuitry, mixed on one substrate, and a manufacturing method thereof.
2. Description of the Background Art
With the improvements toward higher integration and larger capacities in semiconductor devices, particularly in dynamic RAMs (DRAMs), three-dimensionalization of the memory cells have been studied after the 4M (Mega) DRAM generation for the purposes of maintaining soft-error resistance and securing capacitances of the capacitors. The structures for three-dimensional memory cells have been selected as the DRAM generation advances, and they are now being converged into stacked capacitor cells and trench capacitor cells.
In contrast with the trench capacitor cells in which a trench is formed in a silicon substrate to ensure the capacitances of capacitors with the depth, capacitors are stacked on a silicon substrate in the stacked capacitor cells to ensure the capacitances of the capacitors with the height. Typical stacked capacitor cells include the thick-film stacked capacitor cells which have been used from the 16M DRAM generation, the cylindrical capacitor cells which have been used from the 64M DRAM generation, the Fin capacitor cells, the thick-film rough-surface capacitor cells, etc. Among these stacked capacitor cells, a structure and a fabrication process of a DRAM 90 having cylindrical capacitor cells will be described referring to FIGS. 23A to 32B.
FIGS. 23A, 24A, 25A, 26A, 27A, 28A, 29A, 30A, 31A and 32A are partial sectional views showing the memory cell part of the DRAM 90 and FIGS. 23B, 24B, 25B, 26B, 27B, 28B, 29B, 30B, 31B and 32B are partial sectional views showing the peripheral circuit part including sense amps, decoders, etc., formed around the memory cell part in the DRAM 90.
First, in the process step shown in FIGS. 23A and 23B, a field oxide film 2 is selectively formed in a P-type silicon semiconductor substrate 1.
Then P-type impurity ions and N-type impurity ions are selectively implanted by using resist (not shown) as a mask to form a P-type well region 3 in the memory cell part and a P-type well region 3 and an N-type well region 4 in the peripheral circuit part in the P-type silicon semiconductor substrate 1.
Next, a gate oxide film 5 is formed on the P-type well region 3 and the N-type well region 4 in the part where the field oxide film 2 is not formed and gate electrodes 6 are formed selectively on the gate oxide film 5. At this time, word lines 61 are formed on the field oxide film 2 in the same process step as the gate electrodes 6.
Then N-type impurity (As or P) ions are implanted to a low dose (1xc3x971013 to 1xc3x971014 cmxe2x88x922) into the P-type well region 3 right under the gate oxide film 5 in the memory cell part by using the gate electrodes 6 as masks to selectively form N-type source/drain regions 71, 72, 73, and N-type source/drain regions 74, 75 are selectively formed in a similar process in the P-type well region 3 right under the gate oxide film 5 in the peripheral circuit part.
Next, in the process step shown in FIGS. 24A and 24B, an oxide film OX1 is formed all over the surface and resist R1 is formed except on the P-type well region 3 in the peripheral circuit part, and the oxide film OX1 is then etched back by using this resist R1 as a mask to form side wall oxide films 10 on both sides of the gate electrode 6 on the P-type well region 3 in the peripheral circuit part.
Subsequently, by using the gate electrode 6 and the side wall oxide films 10 on the P-type well region 3 in the peripheral circuit part and the resist R1 as masks, N-type impurity ions are implanted to a high dose (1xc3x971015 to 4xc3x971015 cmxe2x88x922) into the N-type source/drain regions 74 and 75 to form N+-type source/drain regions 91 and 92.
Next, after removing the resist R1, in the process step shown in FIGS. 25A and 25B, resist R2 is formed except on the N-type well region 4 in the peripheral circuit part and the oxide film OX1 is etched back by using the resist R2 as a mask to form side wall oxide films 10 on both sides of the gate electrode 6 on the N-type well region 4 in the peripheral circuit part.
Subsequently, by using the gate electrode 6 and the side wall oxide films 10 on the N-type well region 4 in the peripheral circuit part and the resist R2 as masks, P-type impurity (B or BF2) ions are implanted to a high dose (1xc3x971015 to 4xc3x971015 cmxe2x88x922) into the N-type well region 4 to form P+-type source/drain regions 81 and 82.
Next, the resist R2 is removed, and then as shown in the process step shown in FIGS. 26A and 26B, an oxide film is formed all over the surface and an interlayer insulating film 11 is formed by planarization. The interlayer insulating film 11 is referred to as an interlayer insulating film underlying bit lines so that it can be distinguished from other interlayer insulating films.
Next, a bit line contact hole 12 is formed through the interlayer insulating film 11 to reach the N-type source/drain region 72 in the memory cell part.
Next, a polysilicon layer, containing N-type impurities, is formed over the entire surface of the interlayer insulating film 11, and then the polysilicon layer is removed by CMP (Chemical Mechanical Polishing) except in the bit line contact hole 12 to form a polysilicon plug 13 in the bit line contact hole 12.
Next, in the process step shown in FIGS. 27A and 27B, bit line contact holes 14 are formed through the interlayer insulating film 11 to reach the N+ source/drain regions 91 and 92 and the P+-type source/drain regions 81 and 82 in the peripheral circuit part. Then a metal layer of TiN (titanium nitride) or W (tungsten), or a multi-layered film thereof, is formed all over the interlayer insulating film 11 and the metal layer is then removed by CMP except in the bit line contact holes 14 to form metal plugs 15 in the bit line contact holes 14.
Next, in the process step shown in FIGS. 28A and 28B, a metal layer of TiN or W, or a multi-layered film thereof, is formed all over the interlayer insulating film 11 and patterned by photolithography and etching to form metal bit lines 16. The metal bit lines 16 are so patterned that they are connected to the polysilicon plug 13 and the metal plugs 15.
Although the metal bit lines 16 in the peripheral circuit part do not always function only as bit lines, they are so named because they are formed in the same process as the bit lines in the memory cell part. Also, the bit line contact holes 14 are so named because they are connected to the metal bit lines 16, though they are not always connected to bit lines.
Although not shown in FIGS. 23B, 24B, 25B, 26B, 27B and 28B, a TG (Transfer Gate) wiring is formed in the peripheral circuit part in the same fabrication process as the word lines 61 (i.e., the gate electrodes 6), for example. Since the TG wiring is formed in almost the same layer as the gate electrodes 6, it may be electrically connected with the metal bit lines 16 by using the bit line contact holes 14.
That is to say, in the process step shown in FIG. 27B, a bit line contact hole (almost the same as the bit line contact holes 14) reaching the TG wiring through the interlayer insulating film 11 may be formed at the same time when forming the bit line contact holes 14, and then a metal plug 15 is buried also in the bit line contact hole reaching the TG wiring at the same time when the metal plugs 15 are buried in the bit line contact holes 14.
Next, in the process step shown in FIGS. 29A and 29B, an oxide film is formed all over the surface of the interlayer insulating film 11 and an interlayer insulating film 17 is formed by planarization. The interlayer insulating film 17 is called an interlayer insulating film underlying storage nodes so that it can be distinguished from other interlayer insulating films.
Next, storage node contact holes 18 are formed through the interlayer insulating films 11 and 17 to reach the N-type source/drain regions 71 and 73 in the memory cell part at least.
Next, when a conductor layer for the formation of storage nodes is formed all over the interlayer insulating film 17 with N+ polysilicon into which N-type impurities are introduced to a high concentration, for example, the conductor layer for the formation of storage nodes is also buried in the storage node contact holes 18 to form buried layers 31.
Then a thick insulating film is formed all over the surface and then the conductor layer for the formation of storage nodes and the thick insulating film are removed through a process of photolithography and etching, leaving bottom films 19 forming the bottom of the storage nodes and the thick insulating film on the bottom films 19. Now the thick insulating films on the bottom films 19 are called insulating films 26 for the formation of cylindrical capacitors.
Next, in the process step shown in FIGS. 30A and 30B, a conductor layer for the formation of storage nodes is formed again all over the surface and is selectively removed by etch back so that it is left only around the bottom films 19 and insulating films 26 for the formation of cylindrical capacitors. The remaining parts of the conductor layer for the formation of storage nodes form side films 20 serving as side walls of the storage nodes. The bottom films 19 and the side films 20 form storage nodes SN.
Next, only the insulating films 26 for the formation of cylindrical capacitor are removed and a capacitor gate insulating film 21 is formed on the surface of the bottom films 19 and the side films 20 in the process step shown in FIGS. 31A and 31B. Then a conductive film for the formation of cell plate is formed all over the surface and the conductive film for cell plate formation is left only in the memory cell part through a process of photolithography and etching. The remaining conductive film for the formation of cell plate forms a cell plate electrode 22.
Next, in the process step shown in FIGS. 32A and 32B, an oxide film is formed all over the surface and an interlayer insulating film 23 is formed by planarization. The interlayer insulating film 23 is called an interlayer insulating film underlying aluminum wiring so that it can be distinguished from other interlayer insulating films.
Next, an aluminum wiring contact hole 24A reaching the cell plate electrode 22 is formed in the memory cell part and aluminum wiring contact holes 24B reaching the metal bit lines 16 through the interlayer insulating films 23 and 17 are formed in the peripheral circuit part.
Next, when a conductor layer for the formation of aluminum wiring is formed all over the surface of the interlayer insulating film 23, the conductor layer for the formation of aluminum wiring is also buried in the aluminum wiring contact holes 24A and 24B. At this time, buried layers 32 are formed in the aluminum wiring contact holes 24A and 24B. Although a conductor layer for the formation of aluminum wiring is buried in the aluminum wiring contact holes 24A and 24B in this example, it is not limited to aluminum but may be any conductor layer of metal or the like.
Then, through a process of photolithography and etching, aluminum wiring 25 is formed on the interlayer insulating film 23 in the memory cell part and the peripheral circuit part to obtain a DRAM 90 having cylindrical capacitor cells.
Although not shown in FIGS. 28B, 29B, 30B, 31B and 32B, a BL (Bit Line) wiring is formed in the same fabrication process as the metal bit lines 16 in the peripheral circuit part, for example. Since it is formed in almost the same layer as the bit lines 16, the BL wiring and the aluminum wiring 25 may be electrically connected by using the aluminum wiring contact holes 24B.
Generally, with highly-integrated and large-capacity DRAMs, high resolution is required in photolithography, and therefore the focus margin is reduced as trade off.
Accordingly, if the difference in level at the pattern step becomes larger over the focus margin as the degree of integration increases and the capacity becomes larger, it is then very difficult to form wiring by photolithography. Especially, with stacked capacitor cells which are formed by stacking capacitors on a silicon substrate, the difference in level at the pattern step is noticeable, and it is therefore essential to reduce the step height. The interlayer insulating film 11, the interlayer insulating film 17 and the interlayer insulating film 23 therefore undergo planarization as shown in FIGS. 32A and 32B.
However, such a planarization process tends to cause the problem that the thickness of the interlayer films from the aluminum wiring to the silicon substrate becomes too thick, and then it will be quite difficult to make contact holes for connecting the aluminum wiring and the silicon substrate, or the aluminum wiring and the TG wiring. Accordingly, as shown in FIGS. 32A and 32B, in the peripheral circuit part, the aluminum wiring and the silicon substrate, or the aluminum wiring and the TG wiring, are electrically connected by the metal plugs 15 buried in the bit line contact holes 14 through the metal bit lines 16 and BL wiring (not shown).
However, the use of the metal plugs 15 in the peripheral circuit part and the use of the polysilicon plug 13 in the memory cell part may cause such inconveniences as described below.
That is to say, a process of removing the native oxide film at the bottom of the bit line contact holes 14 by etching is required after the bit line contact holes 14 are made and before the metal layer for the formation of metal plugs 15 is formed. This process is performed so as to make ohmic contact between the metal plugs 15 and the silicon substrate and to reduce the contact resistance. At this time, the interlayer insulating film 11 is also etched and the polysilicon plug 13 in the bit line contact hole 12 will partially protrude in the memory cell part.
The protrusion of the polysilicon plug 13 exists only in the memory cell part and not in the peripheral circuit part. When the polishing rate to the polysilicon plug 13 in the CMP is smaller than the polishing rate to the interlayer insulating film 11, trying to remove the protrusion of the polysilicon plug 13 in the CMP process for the formation of the metal plugs 15 will result in over polishing of the interlayer insulating film 11 in the peripheral circuit part. Then the interlayer insulating film 11 in the peripheral circuit part will be recessed like a dish, i.e., the so-called dishing phenomenon. Then the interlayer insulating film 11 cannot be made planar in the entirety of the memory cell part and the peripheral circuit part. This will result in the formation of a step exceeding the step height allowed in the planarization process between the memory cell part and the peripheral circuit part. This may in some cases exceed the focus margin in the formation of the bit lines by photolithography, and then the formation of the bit lines will be very difficult. The dishing phenomenon may occur in the memory cell part, depending on the polishing conditions (hardness of the polishing pad for CMP, kind of the abrasive).
Further, when the protrusion of the polysilicon plug 13 is not perfectly polished away, it may cause processing problem in the formation of the metal bit line 16. Now referring to FIGS. 33 to 35, the processing problem caused by the protrusion of the polysilicon plug 13 in the formation of the metal bit line 16 will be described.
That is to say, in the formation of the metal bit lines 16, resist pattern for bit line formation (called bit line resist pattern) is overlaid on the bit line contact holes 12 by photolithography. At this time, an overlay margin is set in the bit line resist pattern because it may be misaligned. However, a misalignment exceeding the overlay margin may take place. This situation is shown in FIG. 33.
FIG. 33 is a plane view showing the bit line resist pattern RP overlaid on the bit line contact hole 12 (i.e., on the polysilicon plug 13). Although a margin part MP for misalignment is formed in the bit line resist pattern RP, the bit line contact hole 12 is protruding out of the margin part MP.
FIG. 34 shows the section taken along the line AA in FIG. 33. As shown in FIG. 34, the polysilicon plug 13 protrudes from the interlayer insulating film 11 and a metal layer ML of TiN or W is formed thereon as a bit line material. Hence, the metal layer ML has a raised part and the bit line resist pattern RP is formed thereon. The bit line resist pattern RP is formed in the position shifted from the center of the polysilicon plug 13. Accordingly, as shown in FIG. 35, when the metal layer ML is etched by using the bit line resist pattern RP as a mask, the metal layer ML will be left like a side wall at the edge of the polysilicon plug 13 on the side uncovered by the bit line resist pattern RP. This residue of the metal layer ML will come off in the following process steps to form particles.
A first aspect of the present invention is directed to a semiconductor device comprising first and second circuit parts with different structures formed on a semiconductor substrate. According to the first aspect of the present invention, in the semiconductor device, the first circuit part comprises; a first contact hole formed through a first part of an interlayer insulating film formed on the semiconductor substrate, a recessed plug of a conductor having its one end electrically connected to the semiconductor substrate and its other end located in a recessed position in the first contact hole, and a first buried layer composed of almost the same material as an wiring layer formed on the first part of the interlayer insulating film, and buried in the first contact hole to electrically connect the wiring layer and the recessed plug, and the second circuit part comprises; a second contact hole formed through a second part of the interlayer insulating film formed on the semiconductor substrate, and a second buried layer composed of almost the same material as the wiring layer formed on the second part of the interlayer insulating film, and buried in the second contact hole to electrically connect the wiring layer and the semiconductor substrate.
Preferably, according to a second aspect of the present invention, in the semiconductor device, the first contact hole has an enlarged contact part whose opening diameter in a part from a main surface of the interlayer insulating film to the other end of the recessed plug is made larger than an opening diameter of the part in which the recessed plug is buried.
Preferably, according to a third aspect, in the semiconductor device, the recessed plug is composed of polysilicon as a material, and the wiring layer and the first and second buried layers are composed of metal as a material.
Preferably, according to a fourth aspect, in the semiconductor device, the first circuit part is a data holding part for holding data by accumulating charge in a capacitor, and the second circuit part is a peripheral circuit part operating in relation to the data holding part.
A fifth aspect of the present invention is directed to a method for manufacturing a semiconductor device having first and second circuit parts with different structures formed on a semiconductor substrate. According to the fifth aspect of the present invention, the semiconductor device manufacturing method comprises the steps of: (a) forming a first part and a second part of an interlayer insulating film in correspondence with portions to be the first and second circuit parts on the semiconductor substrate; (b) forming a first contact hole reaching the semiconductor substrate through the first part of the interlayer insulating film; (c) filling the first contact hole to form a plug of a conductor having its one end electrically connected to the semiconductor substrate; (d) etching the plug until its other end is recessed in the first contact hole to form a recessed plug buried in the first contact hole; (e) forming a second contact hole reaching the semiconductor substrate through the second part of the interlayer insulating film; and (f) when forming an wiring layer on the first and second parts of the interlayer insulating film, forming a first buried layer of almost the same material as the wiring layer in the first contact hole to electrically connect the wiring layer and the recessed plug, and forming a second buried layer of almost the same material as the wiring layer in the second contact hole to electrically connect the wiring layer and the semiconductor substrate.
Preferably, according to a sixth aspect of the present invention, the semiconductor device manufacturing method further comprises, prior to the step (e), the step of enlarging by wet etching an opening diameter of the first contact hole in a part from a main surface of the interlayer insulating film to the other end of the recessed plug to a size larger than the opening diameter of the part in which the recessed plug is buried to form an enlarged contact part.
Preferably, according to a seventh aspect, in the semiconductor device manufacturing method, the step (c) comprises the step of forming the plug by using polysilicon as a material, and the step (f) comprises the step of forming the wiring layer and the first and second buried layers by using metal as a material.
Preferably, according to an eighth aspect, in semiconductor device manufacturing method, the step (d) comprises the step of etching the plug under an etching condition in which etching selectivity of the plug with respect to the interlayer insulating film is 5 to 20.
Preferably, according to a ninth aspect, in the semiconductor device manufacturing method, the step (d) comprises the step of etching the plug until the other end reaches half of the depth of the first contact hole or lower.
According to the semiconductor device of the first aspect of the present invention, the first buried layer formed of almost the same material as the wiring layer is connected to the recessed plug of a conductor having its other end recessed in the first contact hole so as to electrically connect the wiring layer and the recessed plug. Accordingly, for example, when the recessed plug is formed of a material having physical properties equivalent to those of the semiconductor substrate and the wiring layer and the first buried layer are formed of a material with good electric conductivity, it is possible to prevent applications of physical stresses to the semiconductor substrate and also to reduce the electric resistance between the semiconductor substrate and the wiring layer.
According to the semiconductor device of the second aspect, the opening diameter of the first contact hole in the part from the main surface of the interlayer insulating film to the other end of the recessed plug is larger than the opening diameter of the part in which the recessed plug is buried. Accordingly, even if misalignment occurs when overlaying the wiring layer, i.e. resist pattern, in the formation of the wiring layer in the fabrication process, it is possible to suppress an increase in contact resistance between the wiring layer and the first buried layer by enlarging the opening diameter so that the increase in contact area between the wiring layer and the first buried layer is equal to or larger than the decrease in the contact area between the wiring layer and the first buried layer caused by the misalignment.
According to the semiconductor device of the third aspect, the recessed plug is formed of polysilicon. Accordingly, when the semiconductor substrate is formed of a silicon substrate, the physical properties of the recessed plug and the semiconductor substrate are close, which prevents applications of physical stresses to the semiconductor substrate. Further, since the wiring layer and the first and second buried layers are formed of metal, the electric resistance between the semiconductor substrate and the wiring layer is reduced.
According to the semiconductor device of the fourth aspect, the recessed plug is formed of polysilicon in the data holding part which is designed under strict layout conditions, which considerably prevents applications of physical stresses to the semiconductor substrate. Further, in the peripheral circuit part which is designed under relatively relaxed layout conditions and therefore relatively free from physical stresses, the second buried layer is formed of metal to reduce the electric resistance between the semiconductor substrate and the wiring layer.
According to the semiconductor device manufacturing method of the fifth aspect, a space defined by the other end of the recessed plug and the side wall of the first contact hole is formed in the first contact hole before the wiring layer is formed. For example, even when the native oxide film on the bottom of the second contact hole is removed by etching after the formation of the second contact hole and the interlayer insulating film is removed together at this time, the recessed plug will not protrude. This prevents the problem that when resist pattern is misaligned in the formation of the wiring layer, the material for the wiring layer remains as a residue like a side wall on the edge of a protruding plug and the residue comes off to cause particles. Further, the second buried layer is buried in the second contact hole at the same time as the formation of the wiring layer, which eliminates the necessity of the CMP process which has been required when a plug for the second contact hole is buried in a different process step from the formation of the wiring layer. This solves the problem that the CMP forms a step exceeding the step height permitted in the planarization process between the first circuit part and the second circuit part, which prevents the problem that the step height between the two exceeds the focus margin in the formation of the wiring layer by photolithography to hinder the formation of the wiring layer.
According to the semiconductor device manufacturing method of the sixth aspect, the opening diameter of the first contact hole in the part from the main surface of the interlayer insulating film to the other end of the recessed plug can be made larger than the opening diameter in the part in which the recessed plug is buried. Accordingly, even if misalignment occurs when overlaying the wiring layer, or resist pattern, in the formation of the wiring layer, it is possible to suppress an increase in contact resistance between the wiring layer and the first buried layer by enlarging the opening diameter so that the increase in contact area between the wiring layer and the first buried layer is equal to or larger than the decrease in the contact area between the wiring layer and the first buried layer caused by the misalignment.
According to the semiconductor device manufacturing method of the seventh aspect, the recessed plug is formed of polysilicon. Accordingly, when the semiconductor substrate is formed of a silicon substrate, the physical properties of the recessed plug and the semiconductor substrate are close, which prevents applications of physical stresses to the semiconductor substrate. Further, the wiring layer and the first and second buried layers are formed of metal, which reduces the electric resistance between the semiconductor substrate and the wiring layer.
According to the semiconductor device manufacturing method of the eighth aspect, it is possible to stably form the recessed plug in both of structural and processing aspects by etching the plug under etching conditions in which the etching selectivity of the plug with respect to the interlayer insulating film is 5 to 20.
According to the semiconductor device manufacturing method of the ninth aspect, the other end of the plug is etched until it reaches about half of the depth of the first contact hole, which provides a recessed plug which is stable in structure.
The present invention has been made to solve the above-described problems. In a semiconductor device having a plurality of circuit parts with different structures and in which layers (semiconductor layer, conductor layer) provided above and below an interlayer insulating film are electrically connected through a plug buried in the interlayer insulating film in the respective circuit parts, an object of the present invention is to prevent protrusion of the plug from the interlayer insulating film to prevent formation of a step exceeding the step height permitted in the planarization process between the circuit parts and also to prevent formation of particles due to the protrusion of the plug.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.